FITC Wizard Help

 Welcome to FITC Wizard Help.


Serial Flash Configuration

This screen defines the properties for the Serial Flash attached directly to the PCH for the target platform.

Number of Flash components: Defines the number of flash components connected directly to the PCH's SPI bus. Valid values are 0, 1 and 2. If value is set to 0 only ME region is built. Target Platform HW designer can determine this value by schematic/ layout review.

Flash Component 1 density: Size of the Serial Flash device on the PCH's serial flash bus on chip select 0. (SPI_CS0#) Target Platform HW designer can determine this value.

Flash Component 2 density: Size of the Serial Flash device on the PCH's serial flash bus on chip select 1. (SPI_CS1#) Target Platform HW designer can determine this value.

Total Flash Component Sizes: Shows the total flash space that is available on the PCH's Serial flash bus.

Flash Parts Frequency: Sets the frequency of SPI commands for Hardware Sequencing for Fast read, erase and write commands. Reads only operate at 20 MHz. See PCH SPI programming guide and respective platform design guide for details on serial flash part requirements for 50 MHz. Target Platform HW designer for the design can determine this value.

Dual Output Fast Read Support: This is determines if all serial flash attached to the PCH will support the Single Input Dual Output Fast Read using Opcode 3Bh.

Invalid Instructions: Defines Opcodes for HW sequencing instructions that the Flash Controller should protect against, such as Chip Erase. This byte should be set to 0 if there are no invalid instructions to protect against for this field. Op-codes programmed in the Software Sequencing Opcode Menu Configuration and Prefix-Opcode Configuration are not allowed affected by the Invalid Instructions listed in this section.


Image Source File Configuration

Select the binary files to be used to create a flash image.

Build ME Region Only: This generates the ME region only. This box is only highlighted if the "Number of Flash Components:" on the Serial Flash Configuration screen is set to "0".

ME FW Image: This option enables if a ME FW image will be added to flash image. This option should always be checked.

  • Browse - This will open a file dialog. Select the appropriate ME firmware binary.

BIOS Image: This option enables option of choosing a BIOS image. Only select this option if BIOS is on the serial flash that connects directly to the PCH.

  • Browse - This will open a file dialog. Select the appropriate ME firmware binary.

Intel Integrated LAN Image: Only select this option if using Intel integrated LAN solution. This refers to wired LAN only. If using third party LAN solution, then do not select this option.

  • Browse - This will open a file dialog. Select the appropriate Intel integraed LAN binary.

Total Flash Component size: Defines how much flash space that is available based on the input from the Serial Flash Configuration Screen


Intel (R) ME VSCC Table Configuration

Intel ME VSCC Table Entries are necessary to ensure that the Intel Management Engine can correctly write and erase serial flash. Every flash part that is anticipated to be used on the platform must have an entry in this table, or ME will not function correctly. See PCH SPI programming guide for more information on how to determine the correct VSCC value for the respective flash part.

Entry Name: Human readable text entry to accompany a ME VSCC entry. This is not saved in the Serial Flash image.

Vendor ID: Byte 0 of JEDEC ID (9Fh) from Serial Flash part. See PCH SPI programming Guide for more information on how to obtain the appropriate value.

Device ID 0: Byte 1 of JEDEC ID (9Fh) from Serial Flash part. See PCH SPI programming Guide for more information on how to obtain the appropriate value.

Device ID 1: Byte 2 of JEDEC ID (9Fh) from Serial Flash part. See PCH SPI programming Guide for more information on how to obtain the appropriate value.

Add Entry: This button adds a flash part entry into the VSCC table. Fully fill out the Entry Name, Vendor ID, Device ID 0, Device ID 1 and ME VSCC value before clicking on Add Entry button.

Edit Entry: This button adds a flash part entry into the VSCC table. Click on the target entry flash part before clicking on the Edit Entry button.

Delete Entry: This button adds a flash part entry into the VSCC table. Click on the target entry flash part before clicking on the Delete Entry button.


Intel Integrated LAN Configuration

Configure Intel integrated LAN solution.

Use Intel integrated Wired LAN solution: Ensure this box is checked if using Intel's integrated wired LAN solution. If using 3rd party LAN and NOT Intel Wired LAN solution, ensure that this box is unchecked.

PCIe* port the Intel PHY is attached to: Select the PCIe* port that the Intel PHY is attached to. For Intel Customer mainstream mobile and desktop boards this is port 6. Schematic/layout review will provide the PCIe port the PHY is connected.

Signal LANPHYPC/GPIO12 from PCH is routed to LAN_Disable_N on the Intel wired PHY: This field determines if LANPHYPC/GPIO12 can be used to power gate the Intel PHY.

MACsec Disable: MACsec is a hop-by-hop network security solution. It provides Layer 2 encryption and authenticity/integrity protection for packets traveling between MACsec-enabled nodes of the network. This is not compatible with all Intel vPRO functionality.


Intel ME Application Permanent Disable

Choose Platform Type: This setting will select which PCH platform type the image is being built for: Intel® 6 Series or Intel® 7 Series chipset.

Choose SKU Type: This is a pre-production emulation select for pre-production Intel® 6 Series / Intel® 7 Series chipset. By setting the appropriate SKU, customer can validate specific PCH SKUs. Note: This field has no direct effect production parts, as you cannot change SKUs via this method on production fused parts.

Clicking any permanent selection on this screen will permanently disable that specific feature. Once disabled and flashed on the platform, permanent disable can be modified by FOV mechanism in the manufacturing line as long as descriptor is unlocked and before the fpt -closemnf (before ME End of Manufacturing). After the close of manufacturing, this can only be re-enabled by reflashing the entire ME region.

Ship state is only applicable to Manageability Application. Once set to disabled, it can be re-enabled by the MEBx or in the ME provisioning stage.

Manageability Application: This refers to Intel's ME manageability solutions such as Intel® Active Management Technology and Intel® Standard Manageability. The feature that is enabled depends on PCH/Processor SKU combinations as well as ME provisioning options.

Manageability sub features include:

  • Enable Intel® Standard Manageability / Disable AMT - this is a downgrade to force a Intel® AMT capable system to operate as Intel® Standard Manageability system.
  • TLS - Transport Layer Security - this is necessary to enable encryption with manageability application applications.
  • KVM - This selection turns off the KVM system.

Intel® ME Network Services: This feature permanently disables Intel® ME's ability to communicate with the Intel integrated LAN. If this is set, then Manageability Application is disabled as well.

PAVP: This feature is needed to support HD content playback with Intel integrated graphics solutions.

Intel® Anti-Theft: This feature permanently disables Intel® Anti-Theft Technology. If this is set, then Intel® Anti-Theft Technology will no longer be available.


Intel ME Kernel Configuration Parameters

Processor Emulation: This field allows processor emulation on pre-production processor. This change ME behavior that is based on processor setting. For example, to enable Intel® AMT, then select vPRO capable processor.

Processor Missing: This feature is to let ME signal that processor is missing. There is glue logic that is necessary to have on the board in order to enable the use of this functionality.

Host ME Region Flash Protection Override: This allows Host/BIOS to access the ME region. This is referred to as HMRFPO in BIOS writers guide.

M3 Autotest Enabled: This enables ME M3 auto test during platform early boot.

Power Related Information:

  • Power Package 2 Supported - If this is selected, ME will be on in S0, and will operate in S3, S4 and S5 when required. Power package 2 support requires M3 rail on the platform. ME Wake on LAN requires Power Package 2.
  • M3 Power Rails Availability - If platform design includes a M3 power rail, then this will need to be checked. Platform may choose not to support Power package 2 at OEM/ODM option.
  • Default Power Package - This is the default power package that will operate on the system. This setting can be changed via MEBx or provisioning.
  • Deep Sx Support - This lets ME firmware know that Deep S4/S5 is supported on the platform. This is NOT compatible if you platform is using SUSPWRDNACK.
  • LAN Power Well Configuration - This lets ME know what rail the Intel integrated LAN is on. If using Intel® AMT, then this should be set to SLP_LAN# in order to support low power state functionality. If NOT using Intel LAN, then this field should be set to "Core Well".
    1. Core Well - Power Package 2 Host Wake on LAN and/or ME Wake on LAN are not supported if using this choice.
    2. Sus Well - Power Package 2, ME wake on LAN and Host Wake on LAN are supported, but LAN device is always on regardless of WOL setting.
    3. ME Well - Power Package 2 is supported, but neither ME nor Host Wake on LAN is supported.
    4. SLP_LAN# - Power Package 2, ME wake on LAN and Host Wake on LAN are supported, but LAN is power managed as per WOL setting by PCH.
  • WLAN Power Well Configuration - Should be set to disabled if there is no Intel WLAN connected to the platform. Otherwise specify the appropriate power well.
    1. Disabled - Power Package 2 and/or ME Wake on WLAN are not supported if using this choice. WLAN device is unavailable for use on ME.
    2. Sus Well - Power Package 2 and ME wake on WLAN are supported, but WLAN device is always on regardless of WOL setting.
    3. ME Well - Power Package 2 is supported, but ME Wake on WLAN is not supported. Also supports ME use of WLAN in S0.
    4. Controlled via SLP_LAN# || SLP_ME_CSW_DEV# - Only available if Deep Sx Support is checked. Power Package 2 and ME Wake on WLAN and are supported, but WLAN is power managed as per WOL setting by PCH.
    5. Controlled via SLP_LAN# || SPDA - Only available if Deep Sx Support is NOT checked. Note: HW polarity of SPDA is opposite of SLP_ME_CSW_DEV# Power Package 2 and ME Wake on WLAN and are supported, but WLAN is power managed as per WOL setting by PCH.
  • WCOD Id – This option determines which wireless LAN micro code will be supported in the firmware image.
  • LOCL Id – This option determines which localized language data will be used by the firmware for the secure output screens (Examples: SOL / KVM).

FW Update OEM ID: This field provides the ability to target FWUpdate (FWUpdLcl.exe) by Platform OEM. This ID will ensure that customers can only update a platform with an image coming from the platform OEM. If set to an all zeros, then any input is valid when doing a firmware update.


Manageability Application

Privacy/Security Level: Configures the Manageability Redirection ports.

  • Default - Enables Client Control mode, Remote Configuration and configures all ports with no User Consent required for Redirection.
  • Enhanced - Enables Client Control mode, Remote Configuration and requires User Consent for Redirection.
  • Extreme - Disables Client Control mode, Remote Configuration and Redirection.

USBr EHCI 1 Enabled: Enables KVM to use keyboard and mouse input on USB ports connected to EHCI 1.

USBr EHCI 2 Enabled Enables KVM to use keyboard and mouse input on USB ports connected to EHCI 2.


Intel ME Networking Services Setup

Intel® Services - Used ONLY by Intel® Services. If enabling Intel® Services, refer the MTP User Guide that is available after registration for detail on how to set this field.

PKI DNS Suffix - Determines the DNS Suffix for the Provisioning Sever.


Intel (R) Anti Theft Technology Setup

Allow Unsigned Assert Stolen: Treat as reserved.

Intel® Anti Theft BIOS recovery Timer Enabled: This timer will enable a 30 minute window to allow a firmware / BIOS reflash before the system is powered down.

Flash Protection Override Policy

  • Hard - This option determines if the ME will enter a disabled state to allow full SPI device re-flashing when the manufacturing override jumper (HMFPRO) is set.
    • Always Allowed - Full SPI re-flash will always be allowed regardless of AT enrollment state.
    • Allowed When AT Not Provisioned - Full SPI re-flash allowed if AT has not been enrolled.
  • Soft - This option determines if the ME will enter a disabled state via BIOS based MEI messages and allow ME only region re-flash.
    • Always Allowed - ME region re-flash will always be allowed regardless of AT enrollment state.
    • Allowed When AT Not Provisioned - ME region re-flash allowed if AT has not been enrolled.

ME SMBus MCTP Address: Defines address for 3G NIC card for use with Intel® AT software.

  • Address Enable - Enables the address.
  • Address - SMBus address that the 3G NIC card controller interfaces with Intel® ME.


DMI/PCIe* Configuration

Set DMI and PCH PCIe* configuration.

DMI and Intel(r) Flexible Display Interface Lan reversal: This field should only be set if the layout requires the lanes to be reversed.

PCIe* Lanes 1-4 Configuration: This field must be set to configure the PCIe Ports 1-4 to meet target Platform requirements.

PCIe* Lanes 5-8 Configuration: This field must be set to configure the PCIe Ports 5-8 to meet target Platform requirements.


Thermal Reporting

Thermal reporting is necessary for all platform that requires PCH, Processor and DIMM thermal data to be provided to an external controller (EC, SIO or BMC) on the SMLink1 interface.

3rd Party Thermal Reporting Data Gathering Device is connected to SMLink1: Only check if there is an external controller connected to the PCH SMLink1 bus. Target Platform Hardware designer and BIOS developer will determine if thermal reporting needs to be enabled. Requires two addresses, I2C* address and GP Address. These addresses must be compliant to what is necessary for the external controller.

I2C* address: Used for Writes to the PCH from the external controller. Target Platform Hardware designer and BIOS developer will determine the I2C Target Address. Ensure 3rd Party device is capable of using the I2C Target Address specified here.

GP address: Used for Block Reads from the PCH to the external controller. Target Platform Hardware designer and BIOS developer will determine the I2C Target Address Ensure 3rd Party device is capable of using the GP Target Address specified here.

SMLink1 Thermal Reporting Select: Select between thermal reporting using:

  • Legacy Intel(r) ME FW SMBus based thermal reporting that reports Processor, PCH and DIMMs.
  • HW based PCH only thermal reporting. This would require PECI to be hooked up directly to EC/SIO in order to get processor temperature.


Boot Configuration Options

BIOS Boot Block size: Determined by Target platform BIOS architecture. If BIOS is not on SPI attached directly to the PCH, then this value must be set to 64 KB. If BIOS Image is not provided, then this box will be grayed out. BIOS included in Intel(r) ME firmware KIT uses 64 KB.

Multiple processors: This is only necessary if there are multiple processors are attached to the platform.


Integrated Clock Configuration

Total Number of ICC Profiles: This will increase the number of clock profiles that you have to configure before building the image. Default is 1 if you only have a single clock profile.

ICC Boot Profiles Selected by: Choose either BIOS or Softstrap option. BIOS option has additional BIOS requirements, see BIOS writers guide for more details.

ICC Boot profile: Specifies which boot profile is selected by Softstrap. If BIOS is selecting boot profile, then this parameter is unused.


ICC Profile 0 Single-Ended Clocks

FLEX[3:0]:

  • Clock Enable - Check box to enable output respective Flex clock.
  • Frequency - Changes the respective Flex Clock Frequency.
  • Slew Rate - Changes the respective Flex clock.
  • Frequency - Changes the respective Flex Clock Frequency.
  • Single vs. Double loaded - Changes the series resistor for Flex Clock loading. 17 ohms for Double loaded, 25 for Single loaded.
  • Affected by PCI CLKRUN - Only selectable when respective flex clock is set to 33 MHz. When selected, the respective clock will stop when CLKRUN is asserted.

PCI[4:0]:

  • Clock Enable - Check box to enable respective PCI clock.
  • Slew Rate - Changes the respective Flex clock.
  • Single vs. Double loaded - Changes the series resistor for PCI loading. 17 ohms for Double loaded, 25 for Single loaded.
  • Affected by PCI CLKRUN - Only selectable when respective flex clock is set to 33 MHz. When selected, the respective clock will stop when CLKRUN is asserted.

ICC Parameters: These read only fields change based on wizard screen selections. Can be used to determine with Register definition defined in the FW Bring up Guide.


ICC Profile 0 Platform & Differential Clocks

PEGA:

  • Clock enable - Enables the respective PCI Express* 2.0 jitter tolerant 100 MHz clock.
  • Clock Request Mapping - Configures which GPIO will gate PEGA clock. Default is to not configure clock gating.

PEGB:

  • Clock enable - Enables the respective PCI Express* 2.0 jitter tolerant 100 MHz clock.
  • Clock Request Mapping - Configures which GPIO will gate PEGB clock. Default is to not configure clock gating.

SRCITPXDP:

  • Clock enable - Enables the clock output to Processor XDP port that supports ITP debug functionality.
  • Clock Request Mapping - Reserved.

ICC Boot Mode: Default is Full Clock Integration Mode - NO Overclocking. Only set to YES Overclocking if the platform supports BCLK or DMICLK overclocking.

Display Clock / DP120: Enables 120 MHz Display Port clock output for PCH for eDP.

Graphics: Set this field based upon the graphics capabilities of the target system:

  1. If Integrated graphics only, or Integrated + Down device (Switchable graphics)
  2. Down Device Graphics only - Integrated graphics is disabled in this mode.
  3. External Graphics - PCI express graphics (PEG) only, no discrete or integrated graphics enabled.

SRC[0:7]:

  • Clock enable: - Enables the respective PCI Express* Port 100 MHz clock.
  • Clock Request Mapping: - Configures which GPIO will gate the respective PCIe* clock. Default is to disable clock gating.

ICC Parameters: These read only fields change based on wizard screen selections. Can be used to determine with Register definition defined in the FW Bring up Guide.


Production / Non Production Configuration

Production Mode: Is necessary when the image is going into a manufacturing environment. It has the recommended Flash protection for shipping platforms. When setting to this mode the ME region and descriptor will be locked. When this is selected the FOV Mechanism will not be available. This setting is recommended for manufacturing environments where manufacturing configuration is not necessary.

Production Mode With BIOS Read/Write Access to PDR - This option functions the same as Production Mode with the addition of allowing BIOS Read and Write access to the Platform Data Region for the SPI flash.

Non-Production Mode: This mode requires the use of FPT - closemnf in order to make it ready for shipment. This setting is recommended for R&D phase as well as manufacturing lines that require configuration.

ME Reset Capture: Reflects when ME reset on Wireless controller link. Only available on platforms.

ME Debug LAN Emergency Mode: Enabled ME Debug to operate in emergency mode. See ME Debug documentation for more detail.

ME Debug SMBUs Emergency Mode: Enables and defines the SMBus address that ME Debug works on using the SMBus interface.


Build

Image Output Path: Determines what directory and the name output image will be saved.

Build: Builds the final image specified by Image Output Path.